The present invention relates to a differential amplifier and a latch circuit using the same amplifier and a memory system using the same latch circuit, or more in particular to a memory system using the pipeline technique and a method of reading information therefrom.
The pipeline technique is used widely for high-speed data processing in a logic LSI including a microprocessor. Application of the pipeline technique to the memory LSI to realize a high-speed memory LSI is disclosed, for example, in JP-A-61-237289 and an article entitled "Pipeline Architecture for Fast CMOS BUFFER RAM's" pp. 741 to 747, Journal of Solid State Circuit, June 1990. Specifically, a dynamic random access memory (DRAM) and a static random access memory (SRAM) with latch circuits interposed for provisionally storing a bit of information between a row decoder and a driver circuit, between the driver circuit and a memory array, between the memory array and a plurality of sense amplifiers and between the sense amplifiers and a multiplexer are disclosed.
The conventional memory systems with latch circuits arranged at given points for shortening the cycle time are impossible to improve in speed remarkably.
In other words, the memory system disclosed in JP-A-55-138908 is a DRAM which has a unique operation of rewriting a data. The data rewrite time is normally as long as about twice the access time, and the memory cycle time is dependent on the rewrite time. This prevents the memory cycle time from being shortened even when a latch circuit is interposed between a memory array and sense amplifiers.
The SRAM described in "Pipeline Architecture for Fast CMOS BUFFER RAM", pp. 741 to 747, Journal of Solid State Circuit, June 1990, on the other hand, uses the entire internal signal amplitude as a full amplitude of a CMOS. As a result, the operating time (time required for discharge) of a latch circuit increases, and therefore the cycle time is shortened only slightly by the latch circuit. Also, the number of latch circuits for shortening the cycle time is increased, thereby substantially lengthening the entire access time. Such a SRAM inevitably uses a memory cell having a substantially large cell size, and it is difficult to realize a large-capacity memory due to the chip size.
In the conventional pipeline systems which generally use a latch circuit of a master-slave type, it might be impossible to shorten the cycle time if the delay time of the entire system is shortened due to a large delay time of the circuit.
Further, if the memory cycle time is to be shortened to improve the operating speed, it is necessary to reduce the propagation delay time between the latch circuits in the memory system. In a RAM operating at a very high speed, the amplitude of a memory cell data is normally held at a small value (30 mV, for example) in order to reduce the propagation delay time. It has been impossible in the conventional latch circuits to insert a latch at a point with such a small signal amplitude in a sense amplifier, thereby making it difficult to realize a pipeline RAM with a short cycle time.